In almost any system that switch data between at least one input port and one output port, means for temporarily storing said data while in the transfer from said input port to said output ports, such as FIFOs and frame buffers, forms part of the design.
In synchronous systems, wherein data on the input and output links are often transferred in essentially fixed size frames, each typically being divided into time slots, use of frame buffers are often preferred.
The function of a frame buffer is to store an entire frame of data during a short period of time and to allow for re-ordering of the slots contained therein. A frame buffer may for example be used to store input frames in such a way that an entire frame of slots is written into the frame buffer with the sequence of slots of the input frame unaffected. When outputted, the slots of the frame are collected from the frame buffer in a random, selective order, thereby providing a desired switching. Alternatively, input slots are written into the frame buffer selectively, thereby providing the desired switching, and the so-created frame of slots is then read out as a whole from the frame buffer.
Irrespective of the way in which a frame buffer is used, it is necessary to make sure that new data written into the buffer does not overwrite old data that have not yet been properly read out therefrom, i.e. to ensure so-called buffer consistency. One way to solve this is to synchronize the writing of frames into a frame buffer and the reading of slots from the buffer according to a common frame synchronization signal. However, if there for example is a phase difference between the frame synchronization signal of the components reading data from the buffer and the frame synchronization signal of the components writing data into the buffer, the task of synchronizing the write and read operations in relation to the buffer becomes more complicated and restricted, typically involving hard-locking the frame synchronization signal of the output components to the frame synchronization signal of the input components in a strict manner. Moreover, when for example switching data from one input port to two or more output ports, this synchronizing problem is further complicated.